SACS: A Cache Simulator Incorporating Timing Analysis with Buffer and Memory Management

Abstract

SACS is a cache simulator that provides the user with a wide range of timing information, in addition to providing typical information such as hit and miss rates. The SACS model includes read and write buffers, main memory, and cache memory. In addition. SACS supports a number of buffer and data forwarding policies, as well as the traditional block replacement, write. and write miss policies. SACS also includes a self-testing mode which can be used to debug the program after source-code modification. SACS, Cache memory, Cache memory simulation, Computer architecture, Computer architecture, Simulation.

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Document Details

Document Type
Technical Report
Publication Date
Mar 01, 1994
Accession Number
ADA280472

Entities

People

  • William G. Smith

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Access Time
  • Computer Architecture
  • Computer Programming
  • Computer Programs
  • Computers
  • Computing System Architectures
  • Debugging
  • Electrical Engineering
  • Engineering
  • Guarantees
  • Instruction Set Architecture
  • Microarchitecture
  • Operating Systems
  • Simulations
  • Simulators
  • Statistical Analysis

Fields of Study

  • Computer science

Readers

  • Marine Propulsion Engineering and Naval Architecture
  • Parallel and Distributed Computing.