The Application of Compiler-Assisted Multiple Instruction Retry to VLIW Architectures

Abstract

Very Long Instruction Word (VLIW) architectures enhance performance by exploiting fine-grained instruction level parallelism. In this paper, we describe the development of two compilar assisted multiple instruction word retry schemes for VLIW architectures. In the first scheme, compiler generated hazard-free code with different degrees of rollback capability for uni-processors is compacted by a modified VLIW trace scheduling algorithm. Nops are then inserted in the scheduled code words to resolve data hazards for VLIW architectures. Performance is compared under three parameters: N, the rollback distance for uni-processors; P, the number of functional units; and n, the rollback distance for VLIW architectures. The second scheme employs a hardware read buffer to resolve frequently occurring data hazards, and utilizes the compiler to resolve the remaining hazards. Performance results are shown for six benchmark programs.

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Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1994
Accession Number
ADA281648

Entities

People

  • Shyh-kwei Chen
  • W. Kent Fuchs
  • Wen-mei Hwu

Organizations

  • University of Illinois Urbana–Champaign

Tags

Communities of Interest

  • Space

DTIC Thesaurus Topics

  • Algorithms
  • Celestial Navigation
  • Compilers
  • Computations
  • Computers
  • Detection
  • High Performance Computing
  • Illinois
  • Instructions
  • Military Research
  • Procedures (Computers)
  • Recovery
  • Scheduling (Production)
  • Simulations
  • Splitting

Fields of Study

  • Computer science

Readers

  • Parallel and Distributed Computing.