Fault Sensitivity and Wear-Out Analysis of VLSI Systems
Abstract
This thesis describes simulation approaches to conduct fault sensitivity and wear-out failure analysis of VLSI systems. A fault-injection approach to study transient impact in VLSI systems is developed. Through simulated fault injection at the device level and, subsequent fault propagation at the gate, functional and software levels, it is possible to identify critical bottlenecks in dependability. Techniques to speed up the fault simulation and to perform statistical analysis of fault-impact are developed. A wear-out simulation environment is also developed to closely mimic dynamic sequences of wear-out events in a device through time, to localize weak location/aspect of target chip and to allow generation of TTF(Time-to-failure) distribution of VLSI chip as whole. First, an accurate simulation of a target chip and its application code is performed to acquire trace data(real work load) on switch activity. Then, using this switch activity information, wear-out of the each component in the entire chip is simulated using Monte Carlo techniques
Document Details
- Document Type
- Technical Report
- Publication Date
- Jul 01, 1994
- Accession Number
- ADA283967
Entities
People
- Gwan S. Choi
Organizations
- University of Illinois Urbana–Champaign