Investigation of Modularly Configured Attached Processors with Intelligent Memories

Abstract

A new architecture for high-performance parallel attached processors is described in this paper. Based on this architecture, an attached processor can be implemented as multiple memory-to-memory pipelines, each being constructed with a class of fundamental components. The unique features are that the attached processor can be configured to match a set algorithms and its memory controllers can be programmed to fit the access patterns required by the algorithms. As a result, high utilization of the processing logic for the given sets of algorithms can be obtained. An example based on matrix multiplication is used for illustration. Finally, design issues related to the implementation of the attached processor based on an MCM technology are discussed.

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Document Details

Document Type
Technical Report
Publication Date
Sep 30, 1994
Accession Number
ADA285454

Entities

Organizations

  • University of Texas at El Paso

Tags

Communities of Interest

  • Advanced Electronics
  • Ground and Sea Platforms
  • Materials and Manufacturing Processes
  • Space

DTIC Thesaurus Topics

  • Access Time
  • Algorithms
  • Computations
  • Computer Programming
  • Computers
  • Computing System Architectures
  • Decoding
  • Diagrams
  • Differential Equations
  • Electrical Engineering
  • Instruction Set Architecture
  • Operating Systems
  • Parallel Computing
  • Parallel Processing
  • Signal Processing
  • Simulations
  • Simulators

Fields of Study

  • Engineering

Readers

  • Parallel and Distributed Computing.