HTS Josephson Technology on Silicon with Application to High Speed Digital Microelectronics.
Abstract
Summary of Progress . Task 2-RSFQ Modeling and design - We have identified parasitic inductance as a critical parameter governing the margins and performance of HTS RSFQ devices. Thermal expansion mismatch induced stress limits the overall thickness of HTS films on silicon substrates to under 70 nm. Because this thickness is less than the london penetration depth, typically 150 nm - 400 nm, we expect a substantial kinetic inductance to be associated with wiring and transmission lines. The kinetic inductance associated with the Josephson junctions themselves is still poorly understood. Because of the importance of inductance to overall circuit performance, we have fabricated and measured (Task 3) some dc SQUIDs and RSFQ flip flops incorporating SQUIDs. The estimated sheet parasitic kinetic inductance is given by the formula L sub sq =lambda sub L(2)/d, where lambda sub L is the London penetration depth, d is the film thickness (d much less than lambda sub L) and the current distribution is assumed to be uniform. The total loop inductance in a dc squid can be extracted from the magnitude of the magnetic field induced critical current modulation. We have performed measurements on a SQUID fabricated from a 25 nm thick film grown on an LaAlO3 substrate by the barium fluoride process. The inductance calculated over a wide temperature range are plotted in Figure 1. Similar results for a much smaller SQUID imbedded in an RSFQ flip flop are also shown in the figure. The temperature dependence to the sheet inductance is a signature of substantial kinetic inductance. Since kinetic inductance negatively impacts circuit performance, it is essential that careful quantitative account of all sources of inductance be included in circuit design efforts.
Document Details
- Document Type
- Technical Report
- Publication Date
- Nov 28, 1994
- Accession Number
- ADA288627
Entities
People
- Peter Rosenthal