Novel Field Effect Transistors for Low Power Electronics.
Abstract
The primary objective of this Phase I project is to determine the extent of the significant reduction in power consumption of integrated circuits which may be achieved by utilizing a novel sidegate FET technology. The new FET technology promises to eliminate the Narrow Channel Effect (NCE) which is one of the primary factors limiting the minimum power consumption of integrated circuits. Bv eliminating the NCE, we will be able to scale the device size dramatically and reduce the power consumption by an order of magnitude. The project will assess the power, speed, circuit design, processing, and manufacturability of the new FET technology for both digital and analog circuit applications. In particular, we will extract device parameters from the new ultra-low power FETs fabricated at UVa develop device models, incorporate these models into a new SPICE package (AIM- SPICE), simulate different logic families including DCFL and SCFL, and compare the predicted performance with the standard DCFL and SCFL logic. We will also analyze the gate current leakage and subthreshold slope as the primary factors limiting the noise margins at low power supplies, establish the minimum required bias voltage for reliable operation, and analyze the factors determining the threshold voltage changes from device to device as well as other factors which may limit the yield and integration scale. (jg)
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 16, 1995
- Accession Number
- ADA289929