Algorithms for Categorizing Multiprocessor Communication Under Invalidate and Update-Based Coherence Protocols.

Abstract

In this paper, we present algorithms that characterize the main sources of communication generated by parallel applications under both invalidate and update based cache coherence protocols. The algorithms provide insight into the reference and sharing patterns of parallel programs and into the amount of useless traffic entailed by each coherence protocol. Under an invalidate based protocol, our algorithms classify the data traffic caused by the different types of cache misses. Under an update based protocol, our algorithms not only categorize the data traffic, but also classify update transactions with respect to the sharing patterns that caused them. Although our algorithms deal with numerous hardware features such as finite sized caches and coalescing write buffers, our categorization is widely applicable and can be easily simplified for use in less detailed environments. Our work extends previous categorizations of cache misses in write invalidate protocols, while introducing a new categorization of the coherence traffic in update based protocols.

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Document Details

Document Type
Technical Report
Publication Date
Sep 01, 1994
Accession Number
ADA290022

Entities

People

  • Leonidas Kontothanassis
  • Ricardo Bianchini

Organizations

  • University of Rochester

Tags

Communities of Interest

  • Energy and Power Technologies
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Abstracts
  • Algorithms
  • Application Software
  • Classification
  • Computer Science
  • Computers
  • Data Sets
  • Delphi Method
  • Directories
  • Engineering
  • Information Systems
  • Multiprocessors
  • Object Code
  • Parallel Computing
  • Simulations
  • Simulators
  • Two Dimensional

Fields of Study

  • Computer science

Readers

  • Computer Networking
  • Parallel and Distributed Computing.
  • Systems Analysis and Design