Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic.

Abstract

The dynamic dissipation of CMOS circuits is becoming a major concern for designers of personal information systems and large computers. Here, we present new CMOS logic families, including Split-Level Charge Recovery Logic (SCRL), within which the transfer of charge between the nodes occurs quasistatically, thus having a power consumption that drops quadratically with operating frequency as opposed to the linear drop of conventional CMOS. The technique in these new families rely on explicitly reversible pipelined logic gates to provide the necessary information needed to recover most of the energy used in the computation. We report results of testing the first fully quasistatic 8x8 multiplier chip (SCRL-l).

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Document Details

Document Type
Technical Report
Publication Date
Jun 01, 1994
Accession Number
ADA290054

Entities

People

  • Saed G. Younis

Organizations

  • Massachusetts Institute of Technology

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Artificial Intelligence
  • Circuit Analysis
  • Circuits
  • Crystal Lattice Vibrations
  • Electronics Laboratories
  • Energy Consumption
  • Energy Transfer
  • Failure Mode And Effect Analysis
  • Field Effect Transistors
  • High Electron Mobility Transistors
  • Integrated Circuits
  • Logic
  • Logic Gates
  • Modules (Electronics)
  • P-N Junctions
  • Power Electronics
  • Semiconductors

Fields of Study

  • Physics

Readers

  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.
  • Plasma Physics / Magnetohydrodynamics