Parallel Adaptive Finite Element: Software for Semiconductor Device Simulation,
Abstract
Parallel algorithms and fully functional application codes for 2D and 3D device analysis of semiconductor devices have been demonstrated. Advanced modeling based on a hydrodynamic formulation (HD) of the semiconductor transport equations and using a Galerkin Least Squares Finite Element Method (GLS-FEM) has demonstrated nearly ideal parallel performance for 2D MOS and Bipolar transistor applications across Intel and IBM machines. Parallelization of conventional drift-diffusion (DD) based device solvers has broken new ground in both direct and iterative solvers. A well-known application code, PISCES, has been parallelized and ported across Intel, TMC, and IBM architectures with best results to date that now approach 6.5 GFlops sustained performance on a 128 node IBM SP/2. A prototype 3D code (STRIDE) which uses iterative methods has parallelized preconditioners for ILU(O), ILU(1), and ILUV and achieved excellent benchmarks on both the Intel and IBM machines. A 4.9 million grid problem run on the Intel Delta machine achieved 20% efficiency using 512 nodes and convergent solutions for a highly nonlinear bipolar transistor problem in 20 minutes per bias point. In support of both 2D and 3D TCAD applications, a new geometry-based structure generator called VIP3D was created. Quad- and oct-tree utilities were developed and used to support the gridding of complex IC structures benchmarked in this work. Results of industrial impact and collaborative interactions are also discussed. (AN)
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 12, 1995
- Accession Number
- ADA291149
Entities
People
- K. H. Law
- N. Aluru
- P. M. Pinsky
- R. W. Dutton
Organizations
- Stanford University