Novel Field Effect Transistors for Low Power Electronics.

Abstract

The primary objective of this Phase I project was to determine the extent of the significant reduction in power consumption of integrated circuits which may be achieved by utilizing a novel sidegate FET technology. The new FET technology eliminates the Narrow Channel Effect (NCE) which is one of the primary factors limiting the minimum power consumption of integrated circuits. By eliminating the NCE, we may scale the device size dramatically and reduce the power-delay product by at least an order of magnitude compared to existing transistor technologies. Additionally, the new FET has two gates which can therefore lead to a significant reduction in the transistor count of ICs, as was demonstrated in a simple NOR gate using only two transistors. Finally, the transistor technology is compatible with fiFET circuits for microwave/digital applications. In this Phase I project, the design, fabrication, characterization and modeling of the new transistor was investigated and issues concerning manufacturability were discussed.

Open PDF

Document Details

Document Type
Technical Report
Publication Date
May 15, 1995
Accession Number
ADA294221

Entities

People

  • William C. Peatman

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Circuits
  • Electron Gas
  • Electronics
  • Electronics Industry
  • Electronics Laboratories
  • Energy Consumption
  • Fabrication
  • Field Effect Transistors
  • Integrated Circuits
  • Metal-Semiconductor Junctions
  • Power Electronics
  • Semiconductor Devices
  • Semiconductors
  • Three Dimensional
  • Transistors
  • Two Dimensional

Readers

  • Integrated Circuit Design and Technology.

Technology Areas

  • Microelectronics