Hardware Implementation of a Desktop Supercomputer for High Performance Image Processing.

Abstract

This report presents a CNN monolithic implementation suitable for Very Large Scale Integration. Novel circuit techniques have been investigated, designed and tested for various basic building blocks such as: (1) a transconductance multiplier, (2) a linear resistor based on a multiplier circuit, (3) an OTA based integrator, (4) a hard limiter circuit and (5) YO circuitry based on Switched Capacitor Techniques. The report addresses both circuit design and layout plan issue. It highlights also the trade-offs among different design parameters including power supplies, dynamic range, area and tolerance. The CNN cell consumes approximately 2.5mW of power and occupies around O.25mm2 of area. The IC has been sent for fabrication through MOSIS. Preliminary experimental results of some basic building blocks are encouraging.

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Document Details

Document Type
Technical Report
Publication Date
May 17, 1995
Accession Number
ADA294272

Entities

People

  • Jose P. De Gyvez

Organizations

  • Texas A&M University

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Capacitors
  • Circuits
  • Data Transmission
  • Dynamic Range
  • Electrical Engineering
  • Energy Consumption
  • Engineering
  • Fabrication
  • Image Processing
  • Impedance
  • Integrators
  • Power Supplies
  • Resistance
  • Resistors
  • Simulations
  • Transconductance
  • Very Large Scale Integration

Readers

  • Electronics Engineering
  • Enterprise Information Systems Architecture and Joint Command Capability Interoperability Support.
  • Integrated Circuit Design and Technology.