The M-Machine Multicomputer.

Abstract

The M-Machine is an experimental multicomputer being developed to test architectural concepts motivated by the constraints of modem semiconductor technology and the demands of programming systems. The M-Machine computing nodes are connected with a 3-D mesh network; each node is a multitureaded processor incorporating 12 function units, on-chip cache, and local memory. The multiple function units are used to exploit both instruction-level and thread-level parallelism. A user accessible message passing system yields fast communication and synchronization between nodes. Rapid access to remote memory is provided transparently to the user with a combination of hardware and software mechanisms. This paper presents the architecture of the M-Machine and describes how its mechanisms maximize both single thread performance and overall system throughput.

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Document Details

Document Type
Technical Report
Publication Date
Mar 01, 1995
Accession Number
ADA298187

Entities

People

  • Andrew L Chang
  • Bill Dally
  • Marco Fillo
  • Nicholas P. Carter
  • Stephen W. Keckler

Organizations

  • Massachusetts Institute of Technology

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Access Time
  • Application Software
  • Artificial Intelligence
  • Bandwidth
  • Communication Systems
  • Computer Programming
  • Computers
  • Computing System Architectures
  • Data Transmission
  • Decoding
  • Floating Point Operations
  • Information Systems
  • Instructions
  • Message Systems
  • Multithreading
  • Switches
  • Three Dimensional

Fields of Study

  • Computer science

Readers

  • Parallel and Distributed Computing.

Technology Areas

  • Microelectronics