Digital Test Generation using Multiprocessing.

Abstract

The Sixteen valued Maximized Propagation Lowered Enumeration (SIMPLE) algorithm is modified to execute efficiently within a parallel or multiprocessing environment. SIMPLE was developed to generate test vectors for stuck-at faults in digital logic circuits and executes on a scalar processor. Implementation of the multiprocessing version was not completed, but simulations showed that speedup was nearly linear with the number of processors for detectable and undetectable faults.

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Document Details

Document Type
Technical Report
Publication Date
Sep 01, 1995
Accession Number
ADA299902

Entities

People

  • Carlos R. Hartmann
  • Dennis C. Shiau

Organizations

  • Syracuse University

Tags

Communities of Interest

  • C4I
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Abstracts
  • Air Force
  • Algorithms
  • Circuits
  • Computers
  • Construction
  • Demographic Cohorts
  • Information Science
  • Logic
  • Logic Gates
  • Magnetic Tape
  • Nand Gates
  • Networks
  • Simulations
  • Translators
  • Xor Gates

Fields of Study

  • Engineering

Readers

  • Mathematics or Statistics
  • Operations Research
  • Parallel and Distributed Computing.