Digital Data Rate Interpolator and Modulator. SBIR. Phase 1.
Abstract
This report presents results of using a commercial 2.5G l2xl4 MAC filter chip to accomplish interpolation for radar signal processing. The report also develops a next generation architecture that results in a 500 MSPS digital interpolator and tap delay line. This will allow the replacement of a large quantity of analog signal processing equipment; improving signal quality and channel matching, while reducing costs by $2-4M per system. The interpolator will accept inputs at 10 MSPS complex, provides a fine frequency shift (0.1Hz, lOOdBc), and interpolates the signal up to 320 MSPS (spec), 480 MSPS (goal). A second chip (TAP) is defined that accepts the interpolated clutter return and seeker pulse, delays it 1-128 samples, multiplies them, and adds the result to other tap delay points. The TAP chip may alternatively frequency shift the interpolated signal in 6 MHz steps (90 dHc). The two chips can be used together to build a cable TV head-end by using two chips per 5 MBaud, 64 QAM input.
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 20, 1995
- Accession Number
- ADA300496
Entities
People
- Lars Jorgensen