Construction of a Connectionist Network Supercomputer.
Abstract
Project Highlights. A new digital vector microprocessor architecture has been invented and will soon be available in working systems. This architecture, called Torrent, is ideally suited to a variety of tasks requiring very high performance fixed point calculations. An infrastructure of software tools and techniques has been developed to support the new Torrent architecture. These tools are currently being used to test the chip design and also port applications code to the architecture. Much of the research involved with the VLSI project, including CAD tool improvements, circuits design and library development, has been incorporated in the university curriculum. Network interface test chips have been built to try new ideas for interconnecting processing modes. A link bandwidth of 300 Mbits per second per "tire has been achieved. Several generations of analog auditory preprocessor chips (smart sensors) are working in the lab. Recent design improvements will make it easier to assemble the chips into complete front end systems. A prototype speed recognition system using the Torrent simulator has been demonstrated. This represents a milestone in system design and integration. A locally developed object-oriented language, Sather, is finding wide acceptance in the research community. This work is being extended as Sather for use on parallel computing platforms, including CNS. (KAR) P. 1-2
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 31, 1995
- Accession Number
- ADA301058
Entities
Organizations
- University of California, Berkeley