Synthesis of Timing-Constrained VLSI Systems.

Abstract

Our research investigated the problem of synthesizing timing-constrained systems, with an emphasis on real-time control circuits and communication-intensive systems. Solving the general problem of synthesizing timing-constrained systems requires solutions to subproblems along a broad front from high-level specification to circuit design and implementation. The specific subproblems we investigated were (1) timing specification, analysis and verification, (2) high-performance clocking methodologies, (3) synthesis of reactive embedded systems, and (4) FPGA architectures and design tools for high-performance circuits and interfaces. (AN)

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Document Details

Document Type
Technical Report
Publication Date
Nov 28, 1995
Accession Number
ADA303421

Entities

People

  • Carl Ebeling
  • Gaetano Borriello
  • Lawrence H Snyder
  • Steven M. Burns

Organizations

  • University of Washington

Tags

DTIC Thesaurus Topics

  • Electronic Equipment
  • Embedded Systems
  • Specifications
  • Verification

Fields of Study

  • Computer science
  • Engineering

Readers

  • Database Systems and Applications
  • Integrated Circuit Design and Technology.
  • Operations Research