VHDL Model Verification and Acceptance Procedure,
Abstract
The goal of this procedure is to establish a set of guidelines to be used by the DOD and industry for determining that a VHDL model is a functionally correct representation of the intended unit/device. In addition, this document provides VHDL model developers the means to evaluate their models against a set of criteria that the Government will be using in evaluation whether a VHDL model has captured the necessary design information. The verification procedure consists of six sections. The first section, Scope, provides an overview of the motivation behind the DOD requirement for VHDL models. This section also addresses models that will be archived and the minimal simulation environment needed for model evaluation. The second section, Referenced Documents, explains the order of precedence for reference documents in determining the functionality, timing and operation of the electronic device. Next is the Initial Inspection Section, which is a visual examination of the delivered files for proper documentation and format. The final three sections, Detailed Inspection, Testing and Data Analysis, and the Final Report, includes a detailed examination and execution of VHDL source code, library components, header information and a report that discusses the findings.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 1995
- Accession Number
- ADA304607
Entities
People
- Mark T. Pronobis
- Michael P. Nassif
Organizations
- Rome Laboratory