Design Techniques for the Prevention of Radiation-Induced Latch-Up in Bulk CMOS Processes.

Abstract

Design and layout techniques are described for preventing radiation-induced latch-up in CMOS VLSI ICs using non-radiation hardened bulk CMOS processes. Such ICs are suitable for use in satellites and other systems where proper operation in a radiation environment is critical in the short term, but where long-term survivability is of less importance. Basic radiation effects are discussed, emphasizing areas where bulk CMOS processes are most susceptible. Two custom CMOS VLSI ICs are designed to demonstrate the described techniques. Test plans are developed for testing and evaluating the described ICs using the investigative techniques. (MM)

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Document Details

Document Type
Technical Report
Publication Date
Sep 01, 1995
Accession Number
ADA305822

Entities

People

  • Anne Madsen

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Materials and Manufacturing Processes
  • Space

DTIC Thesaurus Topics

  • Artificial Satellites
  • Environment
  • Radiation
  • Radiation Effects
  • Survivability

Fields of Study

  • Physics

Readers

  • Integrated Circuit Design and Technology.
  • Nuclear and Radiation Engineering.

Technology Areas

  • Space