A CMOS Current-Mode Full-Adder Cell for Multi-Valued Logic VLSI.

Abstract

This thesis describes the design and implementation of a carry save adder cell for multivalued logic VLSI. A four valued system was chosen and the logic was analyzed and minimized using the HAMLET CAD tool. SPICE was used to design and simulate the required behavior of the current mode CMOS circuits. A VLSI test and evaluation integrated circuit was implemented with MAGIC and fabricated through the MOSIS service. The completed IC was tested and evaluated using a specially designed binary to multivalued logic converter and decoder. Engineering modifcations to the original current mode inverter cells used by HAMLET were made leading to significant power savings in a complete design. The fabricated device performed as predicted by SPICE simulation. Exhaustive functional testing produced correct steady-state output signals for all cases of input loadings. Finally, we show HAMLET minimization heuristics are not efficient in the design of adder cells by comparison with an alternative modulo 4 carry save adder cell in current mode CMOS.

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Document Details

Document Type
Technical Report
Publication Date
Sep 01, 1995
Accession Number
ADA306649

Entities

People

  • Robert J. Barton Iii

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Charge Coupled Devices
  • Circuits
  • Complementary Metal-Oxide Semiconductors
  • Computer Science
  • Converters
  • Detectors
  • Electrical Engineering
  • Energy Consumption
  • Engineering
  • Integrated Circuits
  • Inverters
  • Networks
  • Resonant Tunneling Diodes
  • Simulations
  • Steady State
  • Test And Evaluation
  • United States Naval Academy

Fields of Study

  • Engineering

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Integrated Circuit Design and Technology.