GaAs MESFET Static RAM Design for Embedded Applications.
Abstract
The main focus of this thesis is research in novel GaAs static random access memories for embedded applications. The thesis presents several new circuit structures and design methodologies that are needed to achieve higher performance, lower power, process tolerant static RAMs and digital circuits using E/D MESFETs in GaAs. High static power dissipation hinders the integration levels of memories that use GaAs E/D MESFETs. This report presents a new logic style, called power rail logic (PRL), that was invented to reduce some of the standby power of inactive circuits. PRL offers circuits with a smaller area and up to 40% lower power-delay products than can be achieved with DCFL. A test chip containing 32-bit DCFL and PRL barrel shifters was designed, fabricated, and tested. The PRL circuit, which was about 12% smaller, was found to operate 13% faster than the DCFL circuit while consuming an average of 24% less power, resulting in a 34% smaller power-delay product. Finally, this thesis presented the Aurora RAM compiler (ARC) which was developed to generate and characterize highly manufacturable optimized SRAMs using GaAs E/D MESFET technology.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 01, 1994
- Accession Number
- ADA307684
Entities
People
- Ajay Chandna
Organizations
- University of Michigan