Neural Network Models for Yield Enhancement in Semiconductor Manufacturing and Neural Networks for Inverse Parameter Modeling of IC Fabrications Stages.
Abstract
This project utilizes the neurocomputing technology towards modeling semiconductor fabrication processes for which analytical descriptions do not exist. Using data measured on GaAs fabrication lines of microwave circuits, partial fabrication stages as well as the complete process have been modeled. The developed models allow yield estimation and the determination as to which devices/wafers should be continued in the fabrication line. Subsequently, sensitivity analysis can be performed on process input factors to reveal which inputs carry more importance in producing final electronic devices having targeted specifications. The concept of neural network models of fabrication process has also been applied for achieving improved yield of fabricated devices. Process data have been evaluated for principal components and reduced neural network models developed. Perceptron networks have then been inverted and process inputs recentered to maximize the yield. To achieve this, optimization has been performed in the reduced input space. The principal component analysis allows for re-adjustment of actual inputs for maximum yield. The software DESCENT, developed as a part of this project, can be used as a tool for practical design centering for maximum yield. It should be noted that results of modeling and centering, including the DESCENT package, are available to model and improve yield of other fabrication and manufacturing techniques.
Document Details
- Document Type
- Technical Report
- Publication Date
- Feb 25, 1997
- Accession Number
- ADA322882
Entities
People
- Aleksander Malinowski
- Andrzej G. Lozowski
- Gregory L. Creech
- Jacek M. Zurada
Organizations
- University of Louisville