Processor Management in the Tera MTA Computer System,

Abstract

This paper describes the processor scheduling issues specific to the Tera MTA (Multi Threaded Architecture) computer system and presents solutions to classic scheduling problems. The Tera MTA exploits parallelism at all levels, from fine-grained instruction-level parallelism within a single processor to parallel programming across processors, to multiprogramming among several applications simultaneously. Consequently, processor scheduling occurs at many levels, and managing these levels poses unique and challenging scheduling concerns. We describe the processor scheduling algorithms of the user level runtime and operating system and describe the issues relevant to each. Many of the issues encountered and solutions proposed are novel, given the multithreaded, multiprogrammed nature of our architecture.

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1993
Accession Number
ADA324541

Entities

People

  • Gail Alverson
  • Richard Korry
  • Simon Kahan

Tags

DTIC Thesaurus Topics

  • Algorithms
  • Computer Programming
  • Computer Programs
  • Computers
  • Computing-Related Activities
  • Instructions
  • Multiprogramming
  • Multithreading
  • Operating Systems
  • Scheduling (Production)
  • Software Development

Fields of Study

  • Computer science

Readers

  • Parallel and Distributed Computing.
  • Systems Analysis and Design