Memory Management in the Tera MTA Computer System,

Abstract

This paper describes memory scheduling for the Tera MTA (Multi Threaded Architecture) computer system. The Tera MTA is intended to support a mixture of large and small tasks running in parallel, and ensure that they all make progress commensurate with their importance. We describe the memory scheduling algorithms used to schedule these tasks fairly. Some of the issues encountered and solutions proposed are novel, due in part to the highly multiprogrammed nature of our architecture. In particular, we present an algorithm for swapping a set of tasks to and from memory that achieves minimal overhead, largely independent of the order in which tasks are swapped.

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Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1994
Accession Number
ADA324613

Entities

People

  • Burton Smith
  • Cathy Mccann
  • Richard Korry

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Algorithms
  • Bandwidth
  • Computations
  • Computers
  • Dwell Time
  • Instructions
  • Multiprocessors
  • Multithreading
  • Nutrition Disorders
  • Operating Systems
  • Quantum Memories
  • Scheduling (Production)
  • Time Intervals
  • Workload

Fields of Study

  • Computer science

Readers

  • Parallel and Distributed Computing.