Low Engery/Low Noise Elec. Comp. for Mobile Platform Apps.

Abstract

We prototyped Polyfet RF Device's 80V LDMOSFETs on bulk silicon substrates using advanced numerical two-dimensional (2D) finite-element semiconductor process and device simulators and showed excellent agreement between measured and simulated DC and RF parameters. This infrastructure was then used to develop a number of 40V LDMOSFET designs, both on bulk silicon and SOI material, and identify optimum device structures suitable for further development in Phase II. Our Phase I research has shown the SOI LDMOSFETs promise significant improvements in gain, noise figure, efficiency and manufacturing cost compared to bulk devices. These results are highly promising and provide the impetus for further investigation and development.

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Document Details

Document Type
Technical Report
Publication Date
Jun 13, 1997
Accession Number
ADA327031

Entities

People

  • Krishna Shenai
  • S. K. Leong

Organizations

  • University of Illinois at Chicago

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Agreements
  • Amplifiers
  • Bipolar Junction Transistors
  • Efficiency
  • Electric Fields
  • Low Noise
  • Manufacturing
  • Materials
  • Noise
  • Power Amplifiers
  • Power Gain
  • Radio Frequency Devices
  • Resistance
  • Semiconductors
  • Simulations
  • Simulators
  • Two Dimensional

Readers

  • Computational Modeling and Simulation
  • Integrated Circuit Design and Technology.

Technology Areas

  • Microelectronics