Combinational Logic Synthesis Research Report for Advanced Logic Synthesis for Low Power Mobile Applications Project

Abstract

Timed Shannon Circuits have been proposed as a low-power circuit design style 1 with the attractive properties of providing predictable, delay-insensitive low-power dissipation. In this report we present the results of a comprehensive evaluation to compare the designs generated using Timed Shannon Circuits versus those generated by a commercial logic synthesis program (Synergy).

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Document Details

Document Type
Technical Report
Publication Date
Aug 01, 1997
Accession Number
ADA329387

Entities

People

  • Alexander Saldanha
  • Viorica Simion

Organizations

  • Cadence Design Systems

Tags

DTIC Thesaurus Topics

  • Algorithms
  • Capacitance
  • Circuits
  • Construction
  • Diagrams
  • Digital Circuits
  • Dissipation
  • Energy Consumption
  • Information Systems
  • Logic
  • Logic Gates
  • Models
  • Networks
  • Short Circuits
  • Simulations
  • Simulators
  • Standards

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Electronics Engineering
  • Mathematical Modeling and Probability Theory.