12-Bit High Dynamic Range ADC.

Abstract

During this reporting period, detailed preliminary analysis of the maximum ADC sample rate was completed. The results were discussed during a teleconference held on September 4, 1997 (attendees were: 0. Nichols, B. Oyama, S. Nelson, M. Englekirk, and B. Wong). Summaries of the analysis results are shown in Figures 1-1 and 1-2. The primary result of the analysis is a change in three design goals for the 12-bit ADC: (1) increased sample rate (213 Msps); (2) increased input frequency range (130 Mhz to 190 Mhz); (3) relaxed SNR/SFDR for near-full scale inputs (50 dB at Pclip). These changes are reflected in Figure 1-3. In addition, a preliminary chip specification (shown in Figure 1-4) was generated to communicate the detailed ADC requirements versus capabilities.

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Document Details

Document Type
Technical Report
Publication Date
Sep 01, 1997
Accession Number
ADA329455

Entities

People

  • Bert K. Oyama

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Amplifiers
  • Bandwidth
  • Calibration
  • Capacitance
  • Capacitors
  • Conversion
  • Data Rate
  • Dynamic Range
  • Frequency
  • Frequency Bands
  • High Dynamic Range
  • Overload
  • Power Supplies
  • Sine Waves
  • Specifications
  • Waves

Readers

  • Clinical Trial Research.
  • Control Systems Engineering.
  • Integrated Circuit Design and Technology.