A Novel mm-Wave Heterojunction JFET Technology with Suppressed Hole Injection
Abstract
We have developed a device technology using n-AlInAs/GaInAs on InP substrates, where the gate technology incorporates a p-n junction barrier. The p-n junction exists between an undepleted p-type surface layer (p(+)-GaInAs) and the two-dimensional electron gas (2DEC) in the GaInAs channel. The p(+)-2DEG junction provides a sufficiently high gate barrier that exhibits low gate leakage current and a high breakdown voltage. At the same time, the fixed gate-to-channel separation (solely determined by the MBE growth) leads to a reproducible gate barrier height, resulting in high threshold voltage uniformity (sigma(Vth)=13.7mV). The junction barrier gate technology is the best choice of the three available gate technologies (namely insulator barrier gate, Schottky barrier gate, and the p-n junction barrier gate) for InP-based FETs. The low parasitic resistance and low gate leakage current produced state-of-the-art minimum noise figure (Fmin) and associated gain (Ga) of 0.45 dB and 14.5 dB at 12GHz. The combination of reduced gatelength (0.2 micrometers) and reduced parasitic transit delay translated into a unity gain cut-off frequency (ft) of 105 GHz. The low input resistance (due to high acceptor doping in the gate layer) and high Cgs/Cgd ratio (due to a high aspect ratio design) of the JHEMT improved the unity power gain cut-off frequency (fmax) to 220 GHz. This is the highest fmax ever reported for a junction-barrier FET (JFET).
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 01, 1996
- Accession Number
- ADA332544
Entities
People
- Jeffrey B. Shealy
- Umesh Mishra
Organizations
- University of California, Santa Barbara