Delay Fault and Stuck-At Fault Test Generation Using Multiprocessing

Abstract

Digital logic circuits must be tested to assure their correct behavior at the desired clock rate. This report describes an algorithm for generating tests for path delay faults; these faults are models of the faulty switching behavior of digital circuits. The path delay fault test generation system developed here is based on an extension to the Sixteen valued Maximized Propagation Lowered Enumeration (SIMPLE) algorithm, which was originally developed for stuck-at faults test generation. The extension of SIMPLE resulted in a powerful path delay fault test generator with the ability to identify nearly every non-robustly detectable fault in a circuit without resorting to the enumeration phase. A parallel implementation of the test generator was developed using the Parallel Virtual Machine (PVM) communication package.

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Document Details

Document Type
Technical Report
Publication Date
Oct 01, 1997
Accession Number
ADA339149

Entities

People

  • Carlos R. Hartmann
  • Chien-hsing Wu

Organizations

  • Syracuse University

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Air Force
  • Algorithms
  • Circuits
  • Command And Control
  • Computer Science
  • Demographic Cohorts
  • Digital Circuits
  • Fabrication
  • Generators
  • Logic
  • Logic Gates
  • Networks
  • Parallel Computing
  • Parallel Processing
  • Simulations
  • Virtual Machines
  • Xor Gates

Fields of Study

  • Engineering

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Fault Tolerant Diagnosis of Black and White Balloon Isolation Tests Using ¥.
  • Parallel and Distributed Computing.