A Single Chip Low Power Implementation of an Asynchronous FFT Algorithm for Space Applications

Abstract

A fully asynchronous fixed point FFT processor is introduced for low power space applications. The architecture is based on an algorithm developed by Suter and Stevens specifically for a low power implementation. The novelty of this architecture lies in its high localization of components and pipelining with no need to share a global memory. High throughput is attained using large numbers of small, local components working in parallel. A derivation of the algorithm from the discrete Fourier transform is presented followed by a discussion of circuit design parameters specifically, those relevant to space applications. The generic architecture is explained with a survey of the 16 points FFT architecture specific to this project. An implementation, which included a test chip fabricated through MOSIS, is described. Finally, simulation results based on layout extractions are presented and an outline for future work is given.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1997
Accession Number
ADA339655

Entities

People

  • Bruce W. Hunt

Organizations

  • Air Force Institute of Technology

Tags

Communities of Interest

  • Advanced Electronics
  • Counter WMD
  • Cyber
  • Energy and Power Technologies
  • Space

DTIC Thesaurus Topics

  • Air Force Research Laboratories
  • Algorithms
  • Bipolar Junction Transistors
  • Complementary Metal-Oxide Semiconductors
  • Digital Signal Processing
  • Discrete Fourier Transforms
  • Energy Consumption
  • Energy Efficiency
  • Fabrication
  • Integrated Circuits
  • Ionizing Radiation
  • Logic
  • Radiation Effects
  • Semiconductors
  • Signal Processing
  • Simulations
  • Very Large Scale Integration

Fields of Study

  • Engineering

Readers

  • Adaptive Control and Estimation with Uncertainty in Dynamic Systems.
  • Approximation Theory.
  • Integrated Circuit Design and Technology.

Technology Areas

  • Space