Single Event Upset and Latchup Considerations for CMOS Devices Operated at 3.3 Volts

Abstract

A comparison of single event upset and latchup test results for devices operated at several bias levels, from 2.5 V to 6 V, is reported. Vulnerability to SEU increased with decreasing bias, whereas the opposite pattern was observed for SEL. The relationship between threshold SEU vulnerability and bias is not regular, which precludes the use of simple prediction schemes for obtaining the expected vulnerability at 3.3 V from existing 5 V data.

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Document Details

Document Type
Technical Report
Publication Date
Jan 15, 1998
Accession Number
ADA349539

Entities

People

  • J. Quan
  • K. B. Crawford
  • M. Maher
  • Rokutano Koga
  • S. D. Pinkerton
  • S. J. Hansel
  • W. R. Crain

Organizations

  • The Aerospace Corporation

Tags

Communities of Interest

  • Advanced Electronics
  • Space

DTIC Thesaurus Topics

  • Air Force
  • Air Force Facilities
  • Bipolar Junction Transistors
  • Charge Carriers
  • Charged Particles
  • Corporations
  • Electron Holes
  • Electronics
  • Energy Consumption
  • Energy Transfer
  • Microcircuits
  • Numbers
  • Radiation Effects
  • Semiconductors
  • Square Roots
  • Transistors
  • Vulnerability

Fields of Study

  • Physics

Readers

  • Cybersecurity.
  • Electrical Engineering
  • Materials Science and Engineering.