Reliability-Driven CAD System for Deep-Submicron VLSI Circuits
Abstract
This report describes the development of a hierarchical reliability-driven CAD system for deep-submicron VLSI/ULSI circuits. Three general issues are addressed in this report: layout extraction, circuit simulation, and experiment. Conventional layout extractors are not sufficient for use with the reliability-driven CAD tool. Device and interconnect coordinates must be recorded for simulation of the chip temperature profile; parastic devices must be extracted for simulation of ESD events. The chip temperature profile, critical for accurate prediction of electromigration-induced failures and for accurate simulation of circuit delays, can be simulated for the case that the user supplies the input vectors. If the input vectors are unknown, the temperature profile is estimated using the average power consumption as derived through statistical analysis. I/O projection circuits were subjected to ESD stress and the results were used to verify the electrothermal circuit simulation iETSIM. Sub - 0.5 um PMOSFETS were subjected to hot carrier stress and it was observed that the dominant degradation mechanism is different from that seen in longer channel devices. The CAD system has been installed on the World Wide Web to provide greater ease of use and platform independence.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 01, 1998
- Accession Number
- ADA353021
Entities
People
- E. Rosenbaum
- L. P. Yuan
- S. M. Kang
- Tim Li
- Y. K. Cheng
Organizations
- University of Illinois Urbana–Champaign