Micro-Accelerators for Sensor Data Processing

Abstract

A method for accelerating COTS processor performance using processing nodes implemented with advanced reconfigurable integrated circuit devices has been developed. This technique uses emerging Field Programmable Gate Array technologies configured as special purpose processing nodes, integrated into a COTS architecture, to perform the high throughput functions in military sensor processing. Data formats are tailored to provide maximum performance at minimum size, weight, power and cost. Simulations of the approach have been demonstrated using the high computation throughput functions within radar Space Time Adaptive Processing (STAP) algorithms.

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Document Details

Document Type
Technical Report
Publication Date
Oct 01, 1998
Accession Number
ADA356115

Entities

People

  • Michael R. Lucas
  • Richard F. Webb
  • Steven S. Gercken

Organizations

  • Northrop Grumman

Tags

Communities of Interest

  • Materials and Manufacturing Processes
  • Sensors
  • Weapons Technologies

DTIC Thesaurus Topics

  • Algorithms
  • Circuits
  • Computations
  • Computer Programming
  • Computers
  • Data Processing
  • Detection
  • Detectors
  • Field Programmable Gate Arrays
  • Floating Point Operations
  • Integrated Circuits
  • Memory Devices
  • Radar
  • Signal Generators
  • Simulations
  • Synthetic Aperture Radar
  • Target Recognition

Readers

  • Computer Science/Computer Engineering/Data Science/Digital Signal Processing.
  • Parallel and Distributed Computing.

Technology Areas

  • Space