Reliability-Driven CAD System for Deep-Submicron VLSI Circuits

Abstract

This report describes development of simulation tools for analysis of ESD protection circuits, part of our reliability driven CAD system for deep submicron VLSI/ULSI circuits. Conventional layout extraction tools are inapplicable to ESD protection where parasitic devices and non-standard devices such as SCRs play a large role. We have developed a layout extraction tool which produces input decks for the ESD circuit simulation tool iETSIM. Substrate coupling effects impact the behavior of ESD protection circuits. Herein, we present a circuit level model for substrate coupling effects and a substrate resistance extraction methodology. We also present an improved, simplified model for semiconductor resistors which has been implemented in iETSIM.

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Document Details

Document Type
Technical Report
Publication Date
Sep 01, 1998
Accession Number
ADA357355

Entities

People

  • Ching-hon Tsai
  • Elyse Rosenbaum
  • Patrick Juliano
  • Sing-mo Kang
  • Tong Li

Organizations

  • University of Illinois Urbana–Champaign

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Air Force Research Laboratories
  • Algorithms
  • Basic Programming Language
  • Command And Control
  • Computer-Aided Design
  • Couplings
  • Data Sets
  • Electric Fields
  • Failure Mode And Effect Analysis
  • Information Systems
  • Integrated Circuits
  • Power Electronics
  • Resistance
  • Semiconductors
  • Simulations
  • Simulators
  • Standards

Fields of Study

  • Engineering

Readers

  • Computational Fluid Dynamics (CFD)
  • Integrated Circuit Design and Technology.

Technology Areas

  • Microelectronics