Program Slicing of Hardware Description Languages

Abstract

Hardware description languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a myriad of problems in design, simulation, testing, and formal verification. Program slicing is a static program analysis technique that allows an analyst to automatically extract portions of programs relevant to the aspects being analyzed. We extend program slicing to HDLs, thus allowing for automatic program reduction to let the user focus on relevant code portions. We have implemented a VHDL slicing tool composed of a general interprocedural slicer and a front end that captures VHDL execution semantics. This report provides an introduction to the theory of interprocedural program slicing, a discussion of how to slice VHDL programs, a description of the resulting tool, and a discussion of some applications and experimental results.

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Document Details

Document Type
Technical Report
Publication Date
Mar 15, 1999
Accession Number
ADA363556

Entities

People

  • E. M. Clarke
  • M. Fujita
  • S. P. Rajan
  • S. Shankar
  • T. Reps

Organizations

  • Carnegie Mellon University

Tags

DTIC Thesaurus Topics

  • Computer Programming
  • Computer Programs
  • Computer Science
  • Computers
  • Debugging
  • Engineering
  • Graphical User Interface
  • Language
  • Procedural Programming
  • Programming Languages
  • Simulations
  • Software Development
  • User Interface

Fields of Study

  • Computer science
  • Engineering

Readers

  • Computational Linguistics
  • Computational Modeling and Simulation
  • Software Engineering