Standard Analyzer of VHDL Applications for Next Generation Technology (SAVANT)
Abstract
The problem this Phase 2 SBIR effort addressed was the absence of an established, standard intermediate form (IF) for the exchange of VHDL encoded electronic data among CAD systems. This absence has severely constrained basic research environments, and has precipitated the current sub-optimal nature of CAD in VHDL tool development. Our Baseline Program developed this standard intermediate form (IF), as well as a VHDL design environment utilizing it, which is provided to the research community at no cost, and to commercial developers or users under a licensing fee. The SAVANT environment consists of an Analyzer (implementing the IF), a Code Generator, and a System Support Environment (SSE) containing debugger and visualization/analysis tools (called the VHDLyzer Toolkit or VTK). An option task implemented Object Oriented Extensions to VHDL in the SAVANT environment, and assessed their utility and effectiveness. The Phase 2 baseline objectives focused upon developing and validating the SAVANT system (analyzer, code, generator, debugger, visualization tools), and commercializing the resultant technology. The option task objectives addressed implementation of O-O VHDL constructs in SAVANT, and subsequent model selection, implementation and assessment of O-O VHDL performance in the SAVANT environment. All baseline and option task objectives were achieved, except for commercialization. which was partially achieved.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jul 01, 1995
- Accession Number
- ADA364310
Entities
People
- Dale E. Martin
- Herbert L. Hirsch
- Michael W. Shellhause
- Philip A. Wilsey
- Praveen Chawla