Behavioral Fault Modeling in a VHDL Synthesis Environment
Abstract
Integrated circuit designs continue to increase in both size and complexity, making fault simulation and testing more difficult and costly. Computer aided design tools and hardware description languages are now commonly used to represent designs at higher levels of abstraction. However, fault simulation and testing of digital circuits have been historically done using fault models at the gate level or below. A design methodology is needed for performing fault simulation throughout the design process, incorporating fault models at higher levels of abstraction. Use of these higher level fault models has the promise of reducing complexity, providing earlier identification of potential problems, and improving integration of fault simulation into the overall design process. Previous behavioral fault models lack a well defined link to the hardware which they attempt to describe. Though some relationships to possible hardware faults are proposed, there is no detailed analysis to justify these assertions. Approaches based on perturbing language constructs, such as ADD to SUB, do not accurately reflect underlying hardware faults. In order to compensate for this big micro-operation problem, alternate methods such as heuristics are used to supplement test vector sets to increase the equivalent gate level fault coverage. This dissertation proposes a new set of fault models for VHDL behavioral descriptions of combinational logic circuits. These fault models exploit hardware relationships that exist in a design environment which involves synthesis of behavioral descriptions into gate level circuits. A functional analysis technique is used to evaluate the effects of industry standard single stuck line (SSL) faults on gate level implementations. The generalized functional faults are then abstracted into the behavioral domain by examining their relationship with the higher level language construct.
Document Details
- Document Type
- Technical Report
- Publication Date
- May 01, 1999
- Accession Number
- ADA365002
Entities
People
- Ronald J. Hayne
Organizations
- University of Virginia