Advanced Compiler Technology for Scalable Parallel Machines

Abstract

This report presents an extensive empirical evaluation of an interprocedural parallelizing compiler, developed as part of the Stanford SUIF compiler system. The system incorporates a comprehensive and integrated collection of analysis, including privatization and reduction recognition for both array and scalar variables, and symbolic analysis of array subscripts. The interprocedural analysis framework is designed to provide analysis results nearly as precise as full inlining but without its associated costs. Experimentation with this system shows that it is capable of detecting coarser granularity of parallelism then previously possible. Specifically, it can parallelize loops that span numerous procedures and hundreds of lines of codes, frequently requiring modifications to array data structures such as privatization and reduction transformations. Measurements from several standard benchmark suites demonstrate that an integrated combination of interprocedural analysis can substantially advance the capabilities of automatic parallelization technology.

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Document Details

Document Type
Technical Report
Publication Date
Apr 01, 2000
Accession Number
ADA378093

Entities

People

  • Monica Lam

Organizations

  • Stanford University

Tags

Communities of Interest

  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Air Force
  • Air Force Research Laboratories
  • Algorithms
  • Application Software
  • Arrays (Data Structures)
  • Automatic
  • Compilers
  • Computations
  • Computer Programming
  • Computer Programs
  • Computers
  • Information Systems
  • Military Research
  • Privatization
  • Recognition
  • Software Development
  • Standards

Readers

  • Computational Modeling and Simulation
  • Parallel and Distributed Computing.