Avoiding Obsolescence With a Low-Cost Scalable Fault-Tolerant Computer Architecture

Abstract

This new computer architecture can use anything from COTS microcontrollers to the latest high-end processors It is a distributed fault-tolerant architecture that is dynamically reconfigurable in the event of device failures, and is fully programmable in conventional high level languages. By using a simple two-level hierarchy with redundant control processors that configure the I/O processor arrangement, even the failure of several processors will have no effect on data. An example is given of a real-time data acquisition system with a total cost for a 16 channel device with mixed sync/async and proprietary baud rates, of less than $500 in parts. This example system can be reconfigured to any arrangement of 16 or less serial interfaces.

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Aug 23, 2000
Accession Number
ADA384020

Entities

People

  • Josef Schaff

Organizations

  • Naval Air Warfare Center

Tags

Communities of Interest

  • Advanced Electronics
  • Air Platforms
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Acquisition
  • Central Processing Units
  • Computer Architecture
  • Computer Programming
  • Computer Programs
  • Computers
  • Computing System Architectures
  • Data Acquisition
  • Failure Mode And Effect Analysis
  • High Level Languages
  • Kernels (Operating System)
  • Language
  • Microcontrollers
  • Networks
  • Obsolescence
  • Operating Systems
  • Quantum Computing

Readers

  • Computer Science/Computer Engineering/Data Science/Digital Signal Processing.
  • Parallel and Distributed Computing.