SiC Discrete Power Devices
Abstract
A novel planar vertical MOSFET structure, called ACCUFET, which eliminates both the problem of premature oxide breakdown and low inversion layer mobility has been demonstrated at Power Semiconductor Research Center. The contributions of the parasitic JFET regions in the ACCUFET to its forward conduction and forward blocking characteristics are discussed for the first time. A new process for fabrication of high voltage 4H-SiC ACCUFETs has been designed using insights gained. The process induced variations of the key design parameters of an ACCUFET are discussed. The fabrication of devices such as the Junction Barrier Schottky (JBS) diodes and the Junction Field Effect Transistors (JFET) is compatible with this process without the use of any additional mask levels or process steps. The forward conduction characteristics of 4H-SiC ACCUFETs, fabricated on starting material with different epilayer doping and thickness values, are presented. The effect of the key design parameters such as the channel length, the buried JFET region width, and the gate oxide thickness, and the effect of their process-induced variations on the performance of these devices are discussed. Further, an analytical model developed previously for the on-resistance of the devices has been verified with the aid of the experimental results.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 01, 2001
- Accession Number
- ADA385108
Entities
People
- Bayant Jayant Baliga
- Ravi K. Chilukuri
Organizations
- North Carolina State University