F-RISC- A 1.0 GOPS Fast Reduced Instruction Set Computer for Super Workstation and Teraops Parallel Processor Applications

Abstract

The purpose of this contract has been to establish whether Heterojunction Bipolar Transistors or HBT's could be used in design of high clock rate digital computers. Additionally to establish whether HBT devices offer alternatives in case conventional COTS CMOS runs into manufacturing difficulty or fundamental device limitations below 0.1 microns minimum feature size. A demonstration GaAs HBT byteslice chipset for 2 GHz 1 GOPS Fast RISC computer has been fabricated.

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Document Details

Document Type
Technical Report
Publication Date
Apr 25, 2001
Accession Number
ADA390912

Entities

People

  • John F. Mcdonald

Organizations

  • Rensselaer Polytechnic Institute

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Bipolar Junction Transistors
  • Computers
  • Digital Circuits
  • Electronics Industry
  • Electronics Laboratories
  • Heterojunction Bipolar Transistors
  • Instruction Set Architecture
  • Integrated Circuits
  • Logic Gates
  • Manufacturing
  • Materials Science
  • Modules (Electronics)
  • Power Electronics
  • Semiconductor Devices
  • Semiconductors
  • Three Dimensional
  • Two Dimensional

Readers

  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.