The Scalability of Loop-Level Parallelism

Abstract

This report deals with the four main constraints on the scalability of programs parallelized using loop-level parallelism They are as follows: (1) The available parallelism in the algorithm. (2) The availability and scalability of appropriate hardware (including the operating system and the compilers). (3) Limitations in the design of the hardware. (4) The cost of getting into and out of a parallel section of code. This, in turn, will lead to two important discussions: (1) the theoretical limitations on the scalability of shared memory codes; and (2) the role that the choice of hardware and usage policies play in determining the performance of a shared memory code. These discussions will include examples from the author's own work in porting the implicit computational fluid dynamics code F3D from the Cray C90 to a variety of shared memory platforms.

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Aug 01, 2001
Accession Number
ADA393424

Entities

People

  • Daniel M. Pressel

Organizations

  • United States Army Research Laboratory

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Air Force
  • Central Processing Units
  • Computational Fluid Dynamics
  • Computer Programming
  • Computer Science
  • Computers
  • Computing System Architectures
  • Department Of Defense
  • Fluid Dynamics
  • High Performance Computing
  • Materials
  • Materials Science
  • Military Research
  • Operating Systems
  • Three Dimensional

Readers

  • Computational Fluid Dynamics (CFD)
  • Computer Science.
  • Integrated Circuit Design and Technology.