Photonic High-Speed Analog-to-Digital System Technology (PHAST)
Abstract
The goal of the Photonic High-Speed Analog-to-Digital System Technology (PHAST) program was to develop a 10-bit, 10-Gsps analog-to-digital converter (ADC). This objective was to be accomplished in two phases: Phase I with a goal of delivering an S-bit, 10-Gsps prototype system and Phase II which would focus on developing a 10-bit, 10-Gsps brassboard system. The basic approach uses filter elements to perform the processing required to establish the binary word output. The most promising method uses Mach-Zehnder interferometers as its key photonic processing component. Early in Phase I, a 4-bit ADC was fabricated and successfully tested. The 8-bit ADC required the development of a high-speed tunable laser, which was designed and in the process of fabrication when the project was unexpectedly cancelled by DARPA. This document details the progress and preliminary results in the development of the innovative high-speed, high-resolution analog-to-digital converter. It also describes the implementation plan and testing strategy that would have been used to provide the final system to meet the specified PACT program goals.
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 01, 2001
- Accession Number
- ADA397963
Entities
People
- Edward Toughlian
- Fred Riewe
- Guifang Li
- Henry Zmuda
- Patrick Likamwa