Low-Power VLSI Architectures for Error Control Coding and Wavelets

Abstract

This final report provides a brief summary of our research results supported by the above grant during the period from May 1,1998 to November 30, 2001. Our research has addressed design of high-speed, low-energy, low-area architectures for signal processing systems and error control coders. Contributions in the area of error control coding architectures include design of low-energy and low-complexity finite field arithmetic architectures and Reed-Solomon (RS) codecs. High- performance and low-power architectures for low-density parity-check (LDPC) codes have been developed.

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Document Details

Document Type
Technical Report
Publication Date
Oct 12, 2001
Accession Number
ADA398592

Entities

People

  • Keshab K. Parhi

Organizations

  • University of Minnesota

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Abstracts
  • Algorithms
  • Arithmetic
  • Coders
  • Coding
  • Computer Programming
  • Computer-Aided Design
  • Data Transmission
  • Decoding
  • Digital Communications
  • Digital Filters
  • Digital Signal Processing
  • Energy Consumption
  • Frequency Domain
  • Low Density
  • Power Electronics
  • Signal Processing

Fields of Study

  • Engineering

Readers

  • Computer Programming and Software Development.
  • Distributed Systems and Data Platform Development
  • Technical Research and Report Writing.