Envelope: A New Approach to Estimating the Delivered Performance of High Performance Processors

Abstract

Simulating a computer run can be an excellent method for identifying performance bottlenecks and is especially valuable when discussing systems that do not yet exist. Traditional simulations collect a program trace and then have a simulator execute some subset of the trace one instruction at a time. Unfortunately, all of the standard variants of this technique are far too slow to use on jobs for high-end High Performance Computers and Supercomputers. We have developed an approach based primarily on an analysis of the memory access patterns and the number of floating point operations being executed that will estimate the performance of any run in a small fixed amount of time (e.g., a few seconds or less). Experience has shown that the results are nearly always within a factor of 2 of the measured results and frequently are within 15% or better of the measured results.

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Document Details

Document Type
Technical Report
Publication Date
Feb 01, 2002
Accession Number
ADA399723

Entities

People

  • Daniel M. Pressel

Organizations

  • United States Army Research Laboratory

Tags

Communities of Interest

  • Energy and Power Technologies
  • Materials and Manufacturing Processes
  • Space

DTIC Thesaurus Topics

  • Central Processing Units
  • Computational Fluid Dynamics
  • Computer Languages
  • Computer Programming
  • Computer Programs
  • Computers
  • Equations
  • Floating Point Operations
  • High Performance Computing
  • Instruction Set Architecture
  • Instructions
  • Language
  • Military Research
  • Simulations
  • Simulators
  • Standards
  • Supercomputers

Fields of Study

  • Computer science

Readers

  • Computer Science.
  • Instructional Design and Training Evaluation.
  • Operations Research