Very High Speed Integrated Circuits (VHISC) Hardware Description Language (VHDL) Interactive Validation Alchemy (VIVA). Technology and Software for Semiautomated, High Fidelity Validation of VHDL-Related Tools
Abstract
The objective of the VIVA program was to develop a tool to generate a suite of tests to validate the compliance of Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) tools to the standard definition. The test suite is semi-automated to enable maximum flexibility and coverage of the language definition, thus, precluding the introduction of language compliance errors in DoD systems designs that utilize VHDL. The approach includes lexical, syntactic semantic (analysis-time and elaboration-time), functional, and temporal tests. The test suite will include contextual situations and capacity testing in an interactive generation, test and analysis environment, for validating tools. The validation test generation tool development provides a lower cost, more reliable, and maintainable means for DoD/NIST to certify tools as VHDL-compliant. The approach also shows promise for helping automate other NIST certification tasks in the future. The tools can also be made available to VHDL vendors who want to test their newly developed tools for VHDL compliance so they can provide higher quality products to their customers.
Document Details
- Document Type
- Technical Report
- Publication Date
- May 01, 2001
- Accession Number
- ADA404056
Entities
People
- John Willis
- Patrick Gallagher
- Robert Newshutz
- Sathyanarayanan Seshadri
- Senjeev Thiyagarajan