Large Area Si Substrates for InP Based Electronics and Optical Device Manufacturing
Abstract
InP-based materials enable optoelectronic and high speed devices. InP structures are limited in a real size, which greatly adds to the cost of InP devices. Conversely, silicon wafers are an order of magnitude larger and less costly. This STTR program seeks to create device quality InP layers on silicon substrates. The lattice mismatch between Si and InP would normally create defects in the crystal and result in poor material quality. To achieve good InP growth, a thin oxide buffer layer is grown on top of the Si prior to the InP. This oxide layer absorbs the strain mismatch between the two materials. The Phase I has demonstrated InP on Silicon with good structural and optical quality. Optimization of the process will be conducted in Phase II.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 18, 2003
- Accession Number
- ADA415679
Entities
People
- Peter Chow