MorphoSys Project

Abstract

The MorphoSys architecture is a coarse-grain, reconfigurable computing architecture. This program was funded by DARPA in support of the Adaptive Computing Systems (ACS) Technology Initiative. The architecture was successfully functionally prototyped with the fabrication of the M1 chip. This report will review the MorphoSys architecture and the M1 chip. The tools and application mappings are described. The design improvements to the M1 is detailed as the M2 chip design. Additionally, MorphoSys application domains are detailed. Technology transition success through the DARPA Mission Specific Processing Technology Initiative, the MorphoSys related Morpho Technologies venture capital startup, and Motorola licensing agreements are also touched upon. Finally, a program summary is provided.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 2002
Accession Number
ADA416185

Entities

People

  • Nader Bagherzadeh

Organizations

  • University of California, Irvine

Tags

Communities of Interest

  • Advanced Electronics
  • C4I
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Application-Specific Integrated Circuits
  • Central Processing Units
  • Communication Systems
  • Computer Architecture
  • Computer Programming
  • Computer Programs
  • Computers
  • Digital Communications
  • Digital Signal Processing
  • Fabrication
  • Information Systems
  • Instruction Set Architecture
  • Integrated Circuits
  • Multiple Access
  • Target Recognition
  • Two Dimensional
  • Wireless Communications

Fields of Study

  • Computer science

Readers

  • Defense Technology Research and Development.
  • Parallel and Distributed Computing.