Power Estimation and Synthesis for Low Power

Abstract

This document is the final report of the Power Estimation and Synthesis for Low Power. It describes the contributions and achievements of this project. The project explored a wide variety of techniques related to the design of low power CMOS electronic circuits. It explored power estimation techniques, synthesis techniques, macro level design techniques, and low power CMOS logic families. A number of computer-aided design algorithms were implemented to support the various techniques.

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Document Details

Document Type
Technical Report
Publication Date
Aug 01, 2002
Accession Number
ADA416232

Entities

People

  • Kaushik Roy

Organizations

  • Purdue University

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Air Force
  • Air Force Research Laboratories
  • Algorithms
  • Circuits
  • Communication Systems
  • Computational Complexity
  • Computer-Aided Design
  • Computers
  • Department Of Defense
  • Digital Circuits
  • Electrical Engineering
  • Electronic Circuits
  • Energy Consumption
  • Engineering
  • Logic Gates
  • Signal Processing
  • Wiring Diagrams

Fields of Study

  • Engineering

Readers

  • Adaptive Control and Estimation with Uncertainty in Dynamic Systems.
  • Integrated Circuit Design and Technology.

Technology Areas

  • Microelectronics