Picoradio: Communication/Computation Piconodes for Sensor Networks
Abstract
This project addressed the 'system-on-a-chip' implementation of a PicoNode, which can provide all the communication, computation, and geolocation functions necessary for an adaptive distributed sensor-and-monitor network. The program embodied many key principles of DARPA's initiatives in advanced computing, including adaptive computing and power-awareness. The program explored three complete design cycles. Sixty units of PicoNode I (460mW, 18cu.in.) were built. The chip-set for PicoNode II was functionally demonstrated, and a test-board was constructed. At 15mW, the chipset of the second generation represented a 23X improvement over the first generation. Significant progress on the final generation was achieved, including an FPGA version and an energy scavenging power train. Project goals of the final system: 0.15 cu.in. (30x improvement) and 1 mW (460x improvement).
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 02, 2003
- Accession Number
- ADA416233
Entities
People
- Jan M. Rabaey
- Kannan Ramchandran
- M. J. Ammer
- Paul Wright
- Robert Broderson
Organizations
- University of California, Berkeley