Compiler Optimizations for Power-Aware Computing. Volume 1 of 2

Abstract

This final report summarizes work done on the DARPA funded project "Compiler Optimizations for Power Aware Computing." Volume I addresses methodologies invented that can be categorized as software based approaches, hardware based approaches and combined software/hardware based approaches. One of the software based approaches, data remapping, showed a 3.1X energy*delay reduction on a realistic example. One of the hardware based approaches, frequency/voltage scaling of second-level memory, showed a 1.3X energy*delay reduction on a realistic example. A combination of data remapping and frequency/voltage scaling of second level memory showed a 2.6X reduction in energy*delay but also showed the lowest power (energy/time) of any of the approaches considered. Volume II addresses realization of the world's first Wearable Motherboard or an intelligent garment for the 21st Century. The motherboard provides an extremely versatile framework for the incorporation of sensing, monitoring, and information processing devices.

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Document Details

Document Type
Technical Report
Publication Date
Sep 01, 2003
Accession Number
ADA418765

Entities

People

  • Vincent J. Mooney Iii

Organizations

  • Georgia Tech Research Corporation

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Air Force Research Laboratories
  • Algorithms
  • Circuit Boards
  • Compilers
  • Computers
  • Computing System Architectures
  • Embedded Systems
  • Energy Consumption
  • Engineering
  • Frequency
  • Information Processing
  • Instruction Set Architecture
  • Optimization
  • Personal Digital Assistants
  • Power Supplies
  • Semiconductors
  • Simulators

Readers

  • Distributed Systems and Data Platform Development
  • Mathematics or Statistics
  • Parallel and Distributed Computing.